Cell based design in vlsi

Last UpdatedMarch 5, 2024

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The reader is advised to refer to VLSI logic design books for a fundamental understanding of VLSI design and books on hardware description languages like System Verilog and VHDL for basic Oct 7, 2010 · Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. Feb 29, 2024 · Types of Physical Cells. The article explains different types of VLSI design types. Book Author(s): Liming Xiu, What is VLSI physical design? This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “VLSI Design”. Dec 14, 2022 · It covers the importance of standard cell libraries in automatic cell-based designs and the different design file formats used in the SOC design flow. Example − Memory cells, latches, flip-flops and registers. This paper presents two energy-efficient Add-One Carry-Select Adders (A1CSA and A1CSAH) suited for standard-cells synthesis. Lambda Based Design Rules. What is standard cell-based, application-specific integrated 11 circuit (ASIC) design methodology? 8. Provide feature size independent way of setting out mask. In this paper, a new design of True Single Phase Clock (TSPC) scan cell is proposed to eliminate the power consumption in the combinational circuit during scan shifts as well as to lower the clock signal loading. n-well boundary ends at half the cell height. These macro cells are essentially intellectual properties (IP) that can be incorporated into an ASIC design. NP-Separate uses NP cells formed by merging and routing N and P cells having only Mar 18, 2022 · Welcome to our exploration of VLSI (Very Large Scale Integration) design methodologies. Standard cells also facilitate optimization for power consumption, performance, and area (the space occupied on the chip), leading to The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. Wide acceptance. used for synthesis, rapid prototyping, GUI. After going through this post completely May 2, 2011 · Gain-Cell-Based DRAM for Fault-T olerant VLSI Systems Pascal Meiner zhagen 1 , Onur Andıç 2 , Jürg T reichler 2 , and Andreas Burg 1 1 T elecommunications Circuits Laboratory, EPFL, Lausanne A description is given of the logical and physical design of a VLSI bit-serial/word-serial cellular automata-based sorter. With channel formation, the p-type substrate will have to invert itself to n-type near the gate. VLSI Datapath Choices: Cell-Based Versus Full-Custom. The cells are typically optimized full-custom, in order to minimize the delays and area. – The cells are pre-designed for general use and the same cells are utilized in many different chip designs. VDD and GND rail width: 1. 4 Automated Circuit Synthesis and Optimization 16 2. This article delves into the significance of different prerequisites of physical design in VLSI, highlighting its multifaceted importance and the intricacies of the process. As there are many VLSI design software available worldwide that are required at various stages, this article also lists a few software suites that offer hierarchical VLSI design capabilities from top to bottom. Simple for the designer. b) semi-custom design. Then it is synthesized based on technology specific Standard cell libraries. Metal Planning. All these cells are equal in height and can easily fit into the standard cell row. 3. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. Isolation cells are additional cells inserted by the synthesis tools for isolating the buses/wires crossing from power-gated domain of a circuit to its always-on domain. You have to pay your TIME and ATTENTION for that. The rest of this article is organized as follows. If MMMC info not provided, physical design only. Tcl command: set init_mmmc_file {modulo6. What major process technologies are used in today’s design 5 environment? 5. 0278-0070 c 2020 IEEE. We can re-chain power switch based on requirement if the daisy chain has been broken in between due to other design issues. Standard cells are the pre-defined, pre-characterized, and pre-verified cells, Standard cell architecture is defined based on cell height which is determined on the basis of a number of tracks, beta-ratio, pitch, and transistor widths. Voltage scaling is the significant technique to attain power-efficient operation utilizing voltage level shifters. Full custom design approaches succeed in enabling ultra-low energy operation, but are too time intensive for large-scale digital designs. and also few Mar 28, 2014 · Moreover, our migration flow is cell-based, enabling the usage of standard-cell library with all the benefits of modular design, portability, and efficient timing analysis. everything can be dynamically redefined and overridden. Standard cell libraries contain primitive cells required for digital design However, more complex cells that have been specially optimized can also be included. What are the goals of new chip design? 8 6. Vertical grid spacing: 2. 2 Cell-based design techniques 13 2. The discussion begins with a concise overv This tutorial will cover the design aspects and methodology from concept to manufacture of standard cell VLSI circuits. FULL CUSTOM DESIGN2. In contrast to the conven- tionalmethod, the network topology is optimized, or wiring resource consumptionssubject to electromigraton and volt- age drop constraints is mim”mized. Concurrent VLSI Architecture Group Artificial Intelligence Laboratory Massachusetts Institute of Technology and Computer Systems Laboratory Stanford University. For three inputs Nand cell, there can be less drives below 1X. In industry, we generally use the following Physical Cells: In this article, we will discuss the tie cell, Endcap cell, Decap cell, and Spare cell. The layout of a fabric cell utilizes the DWF fabric internally. Volume 1 focuses on design, modelling and simulation, including applications in low voltage and low power VLSI, and post-CMOS devices and Jan 13, 2020 · In this article, we propose a new design methodology, namely, NP-Separate, to reduce the power consumption and area and increase the performance of a VLSI layout more effectively than the standard-cell-based design methodology. clock buffers, clock mux, etc. Decap cells can also be placed in the post route stage also if required. In this paper, we comprehensively review the progress of placement optimization from the perspective of accelerating VLSI May 13, 2013 · The document discusses the physical design process for VLSI circuits. c) gate array design. The sizable number of test points improves the testability of the designs by a very large factor. The critical cells are mostly the cells related to clocks, viz. Used to preserve topological features on a chip. It shrinks the problem scale of the VLSI back-end tools by Isolation Cells. Andrew Liang Ping Chang. g. Dec 30, 2017 · This allows the cells to be abutted end to end and to have the supply rails connect, easing the process of automated digital layout. Jul 1, 1992 · Prelayout timing analysis of cell-based VLSI designs H Youssef, E Shragowitz* and S Sutanthavibul* With the advances m VLSI destgn, chip ttmmo ts becommg dominated by mterconnect delays rather than macro performances For many existing large computer circuits, the mterconnect delays already account for more than one-half of the clock cycle, and the portion of propagation time in the cycle Jan 1, 2013 · Abstract. everything is a command, including structure. Well tap cells connect the nwell to VDD and p-substrate to VSS in order to prevent the latch-up issue. The main purpose of the CAD tools is to implement the so called RTL-to-GDS flow The input to the design process, in most cases, is the circuit description at the register-transfer level Jun 10, 2023 · The scan-based design focuses on connecting these storage elements to form a long serial shift register, commonly known as a scan path. Therefore Abstract. Specify timing libraries for process “corners”. This new design style eliminates the need to synthesise ad hoc wires of any type: May 14, 2007 · Cell-Based ASIC Design Methodology. The library contains the set of logic primitives that are available in the desired design style. The main purpose of the CAD tools is to implement the so called RTL-to-GDS flow The input to the design process, in most cases, is the circuit description at the register-transfer level 4 days ago · Semi custom VLSI design can be cell based or array based. The routing area between instances of the fabric cells utilizes the DWF fabric. Jun 19, 2021 · by VLSI Universe - June 19, 2021 0. In Section III, we present the motivation leading to the NP-Separate design methodology. The video begins by introducing the concept of standard ce Dec 5, 2021 · High quality standard cell layout automation in advanced technology nodes is still challenging in the industry today because of complex design rules. Substrate doping Threshold voltage increases with substrate doping. “Negotiable” means you have to plead your case to the integration leader. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited APPLICATION SPECIFIC INTEGRATED CIRCUITS1. Half the cell height for N and P transistors i. Bistable − Bistable circuits have two stable operating points and will be in either of the states. In the next part (VLSI Jul 14, 2022 · The power efficiency is an extremely essential feature in the modern mobile computing and autonomous sensors node applications. The sorting mechanism is based on the concurrent operation of a number of tesselation-like automata called cellular logic gates (CLGs). Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Worst case and best case timing (min/max delays, etc. • In the full custom design, the entire mask design is done anew without use of any library. It is well known that standard cells have been widely used to implement VLSI circuits in the automation of physical design. Figure 7. Horizontal routing layers: Metal1 and Metal3. This fact requires a change in the approach to timing problems through the design process. The goals of physical design are to minimize signal delays, interconnection area, and power usage. In the realm of VLSI, designers have two primary approaches: Full Custom Design and Semi-Custom Design. VLSI, or Very Large-Scale Integration, embeds thousands of transistors into a single chip in an Integrated Circuit. The resulting netlist normally contains no hierarchy. ((Intervento presentato al convegno 2010 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems. A number of factors affect the threshold voltage: 1. In 1990, VLSI Technology Jan 5, 2018 · The STT-MRAM technology is a promising candidate for future on-chip cache memory because of its high density, low standby power, and nonvolatility. Introduction to VLSI Design, Different types of VLSI design styles: Full custom, standard cell based, gate array based, programmable logic, field programmable gate arrays etc. Essentials VLSI Questions and Answers – Design Styles. CMOS logic: PMOS, NMOS and CMOS, Electrical characteristics, operation of MOS transistors as a switch and an amplifier, MOS inverter. The importance of physical design is explained in the overall SoC design context. Masterworks98 4/25/98 2. In flip-flop-based high-speed designs, maintaining clock skew is a problem, but latches ease this problem. It describes the main steps as partitioning, floor planning and placement, routing, layout optimization, and extraction and verification. Since one major aim of a cell-based design is to minimize Aug 30, 2020 · Decap cells are placed generally after the power planning and before the standard cell placement, that is in the pre-placement stage. Hence, the binding process must exploit the features of such a library, in the search for the best possible implementation. The only problem with decap cells is that these are leaky and Abstract— Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. This design methodology can deliver small, fast, and low-power chips to produce the custom mask set. Aug 29, 2020 · August 29, 2020 by Team VLSI. In the Fabric 1 design methodology, library cells correspond to the standard cells of a standard-cell based design methodology. 6. Level shifters (LSs) with high performance are vital interconnecting circuits to achieve compactness in the multiple-supply voltage low-power VLSI Feb 29, 2024 · VLSI design style impacts the application of the chip, design cycle time, and cost of the project. In which design all circuitry and all interconnections are designed? a) full custom design. 7. Prevents shorting, opens, contacts from slipping out of area to be contacted. 2. This in the Semiconductor industry has become so important to enhance the production of VLSI chips. NP-Separate uses N cells and P cells composed of NFETs and PFETs only, respectively, thereby providing a higher degree Latch based design give you a lot of flexibility but remember nothing comes free. Standard cells are well defined and pre-characterized cells used in ASIC (Application Specific Integrated Circuit) Design flow as basic building blocks. 1 High-level synthesis 16 Jan 1, 1999 · Abstract. Features. Standard cells are designed based on power, area, and performance(PPA), which is used in digital cell libraries. The input SDC can have these constraints on hieracrchical module ports. 2. Metal layer, width, spacing and shielding are negotiable. 4. Energy-efficient fast adders are needed in the design of battery-powered portable devices. Original Preface of the 2010 IAENG International Conference on Electrical Engineering Special Session: Design, Analysis and Tools for Integrated Circuits and Systems. 1) support. 1993). There is no logical function in well tap cell rather than proving a taping to nwell and p-substrate therefore well tap cell It enlarges the back-end solution space of the VLSI design, e. Synthesis results showed During placement and routing, most of the placement tools, place/move logic cells based on floorplan specifications. Multi-Mode/Multi-Corner analysis. Oct 1, 2023 · Synchoros VLSI design style has been proposed as an alternative to standard cell-based design. May 18, 2020 · May 18, 2020 by Team VLSI. Primarily, research in the design of high-performance standard cell libraries has been focused on drive strength selection of various logic gates. Engineers don’t have to design each component from scratch, saving time and effort. For inverters, there can be more drives below 1X. In the modern semiconductor industry IP (Intellectual Property) based VLSI design is trending. Sep 6, 2023 · The term “macro cell” or “mega cell” in the context of ASICs signifies a predefined block that exhibits a significantly higher level of complexity compared to standard cells. May 27, 2014 · VLSI’s design tools included not only design entry and simulation but cell-based routing (chip compiler), a datapath compiler, SRAM and ROM compilers, and a state machine compiler. The isolation list is a list which consists of all the buses/wires that needs isolation cells. It will attempt to provide a broad brush treatment of the subject and show what design aids are available to help designers get their jobs done efficiently and reliably. In cell based design, the designer reuses the cells that have already been designed and stored in the library as a part of the current design. Placement is essential in very large-scale type of cells like cell of a particular drive strength and fine tunes it by picking required cells for a design goal. In Section II, we review the conventional standard-cell-based physical VLSI layout design and transistor sizing. If you see that the constraint is not met, change the constraints by tracing the actual driver and fanin of the ports. Masterworks98 4/25/98 1. e. Earlier, a transmission gate based scan flip-flops is most widely used scan flip-flops. The resultant VLSI design consists of a large number of test points through which test signals on every cell on the IC can be measured or modified to a limited extent. Dec 2, 2022 · Very Large Scale Integration (VLSI) is the process of making Integrated Circuits (ICs) by combining a number of components like resistors, transistors, and capacitors on a single chip. We call our library cells fabric cells. Cell-based layout compaction was claimed in (Yao et al. Physical design transforms the logical VLSI and Post-CMOS Electronics is a useful reference guide for researchers, engineers and advanced students working in the area of design and modelling of VLSI and post-CMOS devices and their circuits. Macro is an essential component in the VLSI design cycle before the final packaged chip is ready to use. The episode at hand provides a comprehensive guide to Standard Cell Characterization in VLSI design for beginners. If the synthesis specifies some driving cell for input ports, and you will also get these in your SDC from synthesis. What are the major approaches of today’s very large scale 9 integration (VLSI) circuit design practices? 7. Design rules based on single parameter, λ. UNIT V CMOS Testing: CMOS Testing, Need for Testing, Test Principles, Design Strategies for Test, Chip Level and Board Level Test Techniques. easy to learn but powerful. Expand. Each Sep 20, 2023 · Standard cells are crucial in VLSI design because they allow for design reusability, optimization, and rapid development. Designing a VLSI Chip includes a few problems such as functional design, logic design, circuit design, and physical design. The paper proposes a novel technique of assessing load using on-chip path delay measurement and hence determines the drive strength of a standard cell in the paths iteratively. The test points are accessed through an on-chip grid of orthogonal probe and sense lines. It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design. Design Options. Low Power Drive Strength Design. The results obtained show that this problem is a critical issue in the coming VL A new testability solution is proposed in which externally accessible test points are pre-designed into cells that comprise the VLSI designs. set_driving_cell. – The development cost of such a design style is prohibitively high. These cells are placed uniformly throughout the design in this stage. The conventional 1T-1 magnetic tunnel junction Mar 16, 2022 · Standard Cell Library for ASIC Design. ) Used to meet timing constraints and calculate delays. These cells are then used in the design by being placed in rows and wired Mar 20, 2018 · In this video I will be explaining you all about the two vlsi design styles : standard cell based design and full custom design and how they all are differe Sep 6, 2023 · A full custom ASIC is a custom-designed integrated circuit where every component is individually inserted in both design and layout. May 29, 2021 · Here the main purpose of the DFT Engineers in VLSI is to incorporate some extra logic structure in the design to make the testing easy, cost effective and efficient design for manufacturing and assembly (DFMA). 35 shows a basic layout diagram of a chip realised with standard cells. Nov 9, 2022 · Macro In VLSI. d) transistor design. Macro cells are the memory cells, intellectual property which an analog design team has designed. The discussion begins with a concise overv VLSI Design 9 Standard Cell Based Design A standard cell based design requires development of a full custom mask set. Mainly here we are going to add some DFT testability features to design of a hardware product. g - Latch-based designs are preferred in case of clock frequency in GHz (in high-speed designs). In the isolation list we specify the clamping value of the nets A new power and ground network design problem for cell-based VLSIS is discussed. These designs are largely reusable in terms of logic function and design layout. Aug 14, 2020 · Power switch cells are placed in the design in daisy chain scheme and their placement starts from bottom left. 4. Standard cells are replaced by synchoros, large grain, VLSI design objects called SiLago (Silicon Lego) blocks. As the technology node scales, especially under 40-nm technology node, STT-MRAM cell design becomes a key issue to approach low power consumption, high access performance, and desirable reliability. , placement and routing, and hence enables some design goals which cannot be achieved based on the original standard cell library, via transistor-level optimizations like diffusion sharing and in-cell signal routing [8]. :) E. 1. Therefore Optimized for timing, some designs can permit a 25-35% increase in the clock rate without any changes in the logic or cell design. It emphasized the pitch-matching of cells and heavily relied on the slicing structure of the layout. All of these impose a physical constraint for layout. Vertical routing layers: Metal2. The tools were an integrated design solution for IC design. The clock gating te Jan 1, 2021 · In this paper, a new design of True Single Phase Clock (TSPC) scan cell is proposed to eliminate the power consumption in the combinational circuit during scan shifts as well as to lower the clock signal loading. 1 Standard cell based ASIC design. Liming Xiu, Dallas, Texas, USA. In array based design, the designer is provided with a chip consisting of configurable logic blocks as generic building blocks. Based on the above discussion, when designing a standard cell library, we need to provide better choices in the drive range below 1X. It also describes various challenges of physical design, Electronic Sequential circuits contain memory elements. View Answer. 8 μm or 6λ. Although many fast adder architectures exist, most of them require transistor-level optimizations that prevent their synthesis in a standard-cell flow. In the realm of VLSI, designers have two primary approaches: Full Custom Design and Semi-Custom Design . The addition of two binary numbers is the fundamental and most often used arithmetic operation on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Some of the important or critical cell's locations has to be pre-defined before actual placement and routing stages. This need is clearly understood by designers of supercomputers and many types of fast clock electronics. Sep 2, 2021 · Integrated clock gating or ICG Cell or Clock gater cell is used to control the clock signal to a sequential element or group of elements. The NP-Separate design methodology for very-large-scale integration (VLSI) design fine-controls the sizes of transistors, thereby achieving significant power, performance, and area improvement compared to the conventional standard-cell-based design methodology. VLSI technology uses _____ to form integrated circuit. 2 μm or 4λ. The total drives below 1X drive vary based on the cell logic. The VLSI circuit that implements the sorting scheme consists of modules of predesigned and precharacterized cells organized in two levels VLSI Design styles: Full-custom, Standard Cells, Gate-arrays, FPGAs, CPLDs and Design Approach for Full-custom and Semi-custom devices, parameters influencing low power design. The Role It is found that the ripple-carry, the carry-lookahead, and the proposed carry-increment adders show the best overall performance characteristics for cell-based design. Cell height: 18 μm or 60λ. Despite extensive prior research on placement, achieving fast and efficient placement remains challenging because of the increasing design complexity. This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Design Styles”. VLSI Design is an iterative cycle. Earlier, a transmission gate based scan flip . DOI: 10. Sequential circuits are of three types −. full unicode (3. 2 Circuit and Layout Design Techniques 12 2. Initially RTL (Register Transfer Language) description of the design is written. VLSI Design flow. Mar 28, 2019 · The efficient design flow presented in this chapter is a crucial aspect of this work. A new design methodology to analyzethe on-chip power supply noise for high-performance microprocessors based on an integrated package-level and chip-level power bus model, and a simulated switching circuit model for each functional block offers the most complete and accurate analysis of Vdd distribution. 7. Standard Cells are custom designed and then inserted into a library. 1 Layout-based design techniques 12 2. tcl} MMMC to be discussed later. Additionally, it discusses different VLSI SoC design styles and the selection criteria depending on the system requirements. This new design style eliminates the need to synthesise ad hoc wires of any type: functional and infrastructural. Macro cells are used to implement complex functions Jan 9, 2023 · Placement is essential in very large-scale integration (VLSI) physical design, as it directly affects the design cycle. Jan 1, 2021 · So, low power testing has become a significant issue to be considered in VLSI circuits. SEMI CUSTOM DESIGN👉👉👉Follow my Telegram Channel to access all PPTS and Notes which are dis Mar 1, 2007 · TLDR. We present an effective approach to tackle the placement legalization problem for such hybrid-row-height designs. Monostable − Monostable circuits have only one stable operating point and even if they are path delays compared to standard-cell-based designs. Enbl_rst. It stands out for its specific cell layout and the use of specific masks for manufacturing. M1,M2 : Local routing (standard cell) M3,M4, M5, M6 : Data and control. 3 Submicron VLSI Design 15 2. 3 Implications 15 2. In this approach, all of the commonly used logic cells are developed, characterized and stored in a standard cell library. This is achieved by utilizing multiplexors and a mode control signal, as illustrated in Figure 1. Search for more papers by this author. As the doping increases, a higher bias is required to move the majority carriers away from the channel region. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. In a general sense, a sequential circuit consists of a combinational circuit accompanied by storage elements. 1145/1973009. A technique for the structural synthesis of VLSI circuits is presented. –Design, layout and evaluation of a register file •Use Cadence layout software, HSpice simulation §Lab Exercise 2 –Design and evaluation of an ALU with standard cell libraries •Cadence schematic editor, Synopsys static timing analysis, Cadence place-and-route §Lab Exercise 3 –RTL/HDL level design and evaluation of bus controller • The standard-cells based design is often called semi custom design. The standard cell is also known as the polycell. Typical 8 layer metal layer allocation. Commercial standard cell libraries and very-large-scale-integration (VLSI) design flows enable a fast design methodology At the heart of VLSI lies the intricate process of physical design, a crucial step that transforms logical circuit representations into tangible semiconductor chips. This episode offers a comprehensive guide to understanding standard cell libraries in VLSI design. 4 μm or 8λ Offset is 1. Minimum feature size is defined as 2 λ. 5 Cell-Based Layout Implementation. 1 Multilevel metal routing 15 2. Optimizations can be performed at each step to improve the 6. Jun 7, 2022 · This chapter introduces system on chip (SoC)s and its design trends. 3 Implications 16 2. VLSI spun off the CAD and Library operation into Compass Design Automation. Mar 18, 2022 · Welcome to our exploration of VLSI (Very Large Scale Integration) design methodologies. This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. This design style offers maximum design freedom, enabling optimal performance, size, and power consumption. The technique uses a Genetic Algorithm which utilises a library of devices for the synthesis procedure which proved successful in searching a highly complex space of structures by producing designs which satisfy a multiple output circuit criteria which, in addition to satisfying the functionality constraint for each of the Jan 9, 2023 · This paper comprehensively review the progress of placement optimization from the perspective of accelerating VLSI physical design, and introduces the development of placement optimizers, including algorithm improvements and computational acceleration, pointing out that these two aspects will jointly promote accelerating VLT physical design. 1973078 Corpus ID: 8200928; Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems @inproceedings{Meinerzhagen2011DesignAF, title={Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems}, author={Pascal Andreas Meinerzhagen and Onur Andiç and J{\"u}rg Sep 19, 2022 · In a traditional or normal standard cell-based design flow, the implementation steps shown in Figure 3a are followed, which includes: (a) importing a floor-planned, power-planned design, (b) placing the standard cells, (c) synthesizing the clock tree, and (d) routing the design. In this paper we introduce an automatic standard cell layout generator called NVCell that can generate layouts with equal or smaller area for over 90% of single row cells in an industry standard cell library on an advanced technology node. A new cell-based design paradigm that mixes short rows and tall rows in a layout has emerged to better optimize power, performance and area. 2 Interconnect delay 16 2. Tools command language (Tcl, tickle) script language. In this design style, an RTL description of the circuit is synthesised and mapped onto a number of standard cells which are available in a library, see Sect. There are four pins in the power switch as per below: Enbl_few. TEXT BOOKS: 1. xz kq hs vl sy zh cp eb al ha